Methods and apparatus for correction of 2-3 field patterns

ABSTRACT

Systems and methods are provided for allowing a user to correct a discontinuous 2-3 field sequence within a disrupted video signal. A 2-3 field pattern fixer can be operated in a one-pass mode and/or a two-pass mode. In the one-pass mode, the disrupted video signal is analyzed to generate correction information, which is used to correct the disrupted video signal as it passes through the 2-3 pattern fixer, resulting in an undisrupted video signal with a continuous 2-3 field sequence. In the two-pass mode, the disrupted video signal is analyzed to generate correction information, which is then stored. This correction information is then used to correct a duplicate of the disrupted video signal, resulting in an undisrupted video signal with a continuous 2-3 field sequence. In this connection, the 2-3 field pattern fixer includes a field sequence detector, a field sequence analyzer, a field sequence generator and a multiple delay tap circuit. The field sequence detector generates field difference values in response to receiving the disrupted video signal. The field sequence analyzer analyzes these field difference values to determine one or more discontinuities within the discontinuous 2-3 field sequence. The field sequence generator generates one or more field sequence correction signals in response to this analysis. The multiple delay tap circuit applies these correction signals to a video signal to generate an undisrupted video signal having a continuous 2-3 field sequence. The 2-3 field pattern fixer can optionally includes a First-In-First-Out (FIFO) memory and a time code comparator, which can be used to store a multitude of the correction signals during the first pass of the two-pass mode, and for synchronizing the application of each of the correction signals to the duplicated disrupted video signal during the second pass of the two-pass mode.

RELATED APPLICATIONS

This application is a continuation of U.S. Ser. No. 10/430,608, filedMay 5, 2003, now issued as U.S. Pat. No. 7,139,029, which is acontinuation of U.S. Ser. No. 09/295,936, filed Apr. 21, 1999, issued asU.S. Pat. No. 6,559,890, both of which are fully incorporated herein byreference.

FIELD OF THE INVENTION

This invention relates to methods and systems for processing videotape,and more particularly to correcting a discontinuous 2-3 field patternthat resides on the videotape.

BACKGROUND OF THE INVENTION

In general, telecine machines that operate at 60 field/sec (actually,59.94 fields/sec) employ a 3:2 pulldown convention to convert filmmedia, which runs at 24 frame/sec (actually, 23.976/sec), to videomedia, which runs at 60 television field/sec (actually, 59.94fields/sec). Specifically, a two-field video sequence and a three-fieldvideo sequence are alternately generated, with each field sequencecorresponding to a film frame. These video fields are interlaced in thatthe film frames are scanned, such that alternating odd and even fieldsare generated, with the lines of the odd fields interleaved with thelines of the even fields. For example, a film frame can be scanned togenerate a two-field video sequence characterized by an even field andthen an odd field (even/odd). The next film frame can be scanned togenerate a three-field video sequence characterized by an even field,then an odd field, and then an even field (even/odd/even). Therespective first and second even fields in this three-field videosequence are duplicates. The next film frame can be scanned to generatea two-field video sequence characterized by an odd field and then aneven field (odd/even). The next film frame can be scanned to generate athree-field video sequence characterized by an odd field, then an evenfield, and then an odd field (odd/even/odd). The respective first andsecond odd fields in this three-field video sequence are duplicates.This pattern then repeats for the next four film frames and so on.

The two/three-field video sequence is sometimes disrupted, such as,e.g., when the video is edited without regard to the video sequence.These disruptions in the video sequence can cause difficulties duringprocessing that requires manipulation of the two/three-field sequence.For example, it is sometimes desired to convert 525 line, 60 fields/secvideo to 625 line, 48 fields/sec video. During this procedure, thetwo/three-field video sequence is converted to a repeating two-fieldvideo sequence by removing the duplicate field from each of thethree-field video sequences, and, if needed, swapping the order of thetwo-field video sequence, thereby generating a repeating two-field videosequence characterized by an even field and then an odd field throughthe entirety of the video (even/odd), or alternatively, an odd field andthen an even field through the entirety of the video (odd/even). The 525line resolution of the 525 line, 60 field/sec video is then interpolatedto produce the 625 line, 48 field/sec video with 625 lines ofresolution. The resulting 625 line, 48 field/sec video is recorded at 24frames/sec, which is then played at 25 frames/sec, which is the normal625 line, 50 field/sec video when viewed. When there is a disruption inthe two/three-field video sequence prior to conversion, the two-fieldsequence subsequent to conversion will sometimes change dominance. Thatis, the repeating odd/even video sequence changes to a repeatingeven/odd video sequence. Because a television system cannot process anodd/odd video sequence (or an even/even video sequence), an even field(or odd field) by itself, or an even/odd/even video sequence (or anodd/even/odd video sequence) must be located at the change in dominance.As a result, the video is degraded.

Another example of a process that requires the manipulation of thetwo/three-field video sequence is the conversion of video to a digitalvideo disk (DVD). To save memory, the two/three-field video sequence isconverted to a repeating two-field video sequence in much the samemanner described above. The two-field video sequence is then compressedinto a motion pictures expert group (MPEG2) format. The DVD player thenrestores the two/three-field video sequence during playback on thetelevision system. Again, however, during conversion, the fielddominance of the two-field video sequence may change, thereby degradingthe DVD.

Thus, it would be desirable to provide methods and systems to correct adisrupted two/three-field video sequence.

SUMMARY OF THE INVENTION

This present invention comprises novel methods and systems forcorrecting a discontinuous 2-3 field sequence within a disrupted videosignal. A 2-3 pattern fixer constructed in accordance with the presentinvention can be operated in a one-pass mode and/or a two-pass mode. Ina one-pass mode, the disrupted video signal is analyzed to generatecorrection information, which is used to correct the disrupted videosignal as it passes through the 2-3 pattern fixer, preferably in realtime, resulting in an undisrupted video signal with a continuous 2-3field sequence. In a two-pass mode, the disrupted video signal isanalyzed to generate correction information, which is then stored. Thiscorrection information is then used to correct a duplicate of thedisrupted video signal, resulting in an undisrupted video signal with acontinuous 2-3 field sequence.

In a preferred embodiment of the present invention, a 2-3 field patternfixer includes a field sequence detector, a field sequence analyzer, afield sequence generator and a multiple delay tap circuit. The fieldsequence detector receives the disrupted video signal and generates aseries of field difference values in response thereto by sequentiallycomparing each of the fields with a field two fields previous. The fieldsequence analyzer analyzes the series of field difference values andgenerates field sequence to determine one or more discontinuities withinthe 2-3 field sequence of the disrupted video signal. The field sequencegenerator uses this information to generate field sequencereorganization information in the form of a correction signal. In thepreferred embodiment, the correction signal comprises a sequence ofdelays. The correction signal is preferably generated, such that acumulative delay within the undisrupted video signal is minimized andthe number of odd field delays are minimized. The multiple delay tapcircuit then applies the correction signal to a video signal to generatean undisrupted video signal having a continuous 2-3 field sequence. Thatis, selected fields of the disrupted video signal or duplicate of thedisrupted video signal are delayed in accordance with the correctionsignal, thereby resulting in the undisrupted video signal. The multipledelay tap circuit can optionally include at least one cross-fader tocross-fade between an odd-delayed field and an even-delayed field,thereby minimizing any blur caused by odd field delays.

This particular embodiment of the 2-3 field pattern fixer can beoperated in the one-pass mode. In this connection, the disrupted videosignal is analyzed to determine one or more discontinuities with thediscontinuous 2-3 field sequence. The discontinuities can be determinedby detecting a scene change and a phase change within the 2-3 fieldsequence. Field sequence reorganization information, and in particular,correction signals are then generated based on these discontinuities.These correction signals are then applied to the disrupted video signalas it passes through the 2-3 field pattern fixer, thereby generating anundisrupted video signal having a continuous 2-3 field sequence from thedisrupted video signal.

The 2-3 field pattern fixer can optionally include a first-in-first-out(FIFO) memory and a time code comparator, allowing the 2-3 field patternfixer to operate in a two-pass mode. The FIFO is coupled between thefield sequence generator and the multiple tap delay circuit and canstore several correction signals. The time code comparator isoperatively coupled to the FIFO and the multiple delay tap circuit tocoordinate the timing of the correction signals as they are input intothe multiple delay tap circuit. The time code comparator receives at afirst input a current time code of the duplicated disrupted videosignal, and at a second input, a trigger time code generated in thefield sequence generator and stored in the FIFO. The trigger time codecorresponds with the time code during which the next correction signalin the FIFO will be initially applied to the duplicated disrupted videosignal. In response thereto, the time code comparator generates atrigger signal that is input into the FIFO and the multiple delay tapcircuit.

In the two-pass mode, the disrupted video signal is analyzed during thefirst pass to determine one or more discontinuities with thediscontinuous 2-3 field sequence. Field sequence reorganizationinformation, and in particular, correction signals and correspondingtrigger time codes are then generated based on the discontinuities andassociated time codes. These correction signals and correspondingtrigger time codes are stored in the FIFO. During the second pass, theduplicated disrupted video signal is received by the multiple tap delaycircuit. When the current time code of the duplicated disrupted videosignal and the first trigger time code match, the time code comparatorsends a trigger signal to the multiple delay tap circuit to beginapplying the correction signal to the duplicated disrupted video signal.The trigger signal is also sent to the FIFO to advance the nextcorrection signal for subsequent use by the multiple delay tap circuit,and the next trigger time code to the time code comparator. When thecurrent time code of the duplicated disrupted video signal matches thenext trigger time code, the time comparator again sends a trigger signalto the multiple delay tap circuit to begin applying the next correctionsignal. This process is then repeated until the last correction signalin the FIFO has been applied to the duplicate disrupted video signal.Each of the correction signals are preferably applied to the duplicateddisrupted video signal at a field rate equal to the field rate of thedisrupted video signal.

Other and further objects, features, aspects, and advantages of thepresent invention will become better understood with the followingdetailed description of the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate both the design and utility of preferredembodiments of the present invention, in which:

FIG. 1 is a block diagram of a preferred embodiment of a 2-3 fieldpattern fixer constructed in accordance with the present invention;

FIG. 2 is table showing the derivation of first and second continuous2-3 field sequences from a discontinuous 2-3 field sequence byrespectively employing two correction signals;

FIG. 3 is a plot of field difference values generated from each of thefields of the discontinuous 2-3 field sequence depicted in FIG. 2,wherein the phase and edit point of the discontinuous 2-3 field sequenceare particularly indicated by the field difference values; and

FIG. 4 is a block diagram of a compensatory multiple delay tap circuit,which can be employed in the 2-3 field pattern fixer of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a schematic representation of a 2-3 field pattern fixer 10,which is configured to receive, at an input IN, a disrupted video signalVIDEO_(IN) having a series of fields arranged in a discontinuous 2-3field sequence, i.e., a 2-3 field sequence having at least onediscontinuity, and transmit, at an output OUT, an undisrupted videosignal VIDEO_(OUT) having a series of fields arranged in a continuous2-3 field sequence, i.e., a 2-3 field sequence having nodiscontinuities. The 2-3 field pattern fixer 10 is configured toselectively operate in either a one-pass mode or a two-pass mode. In theone-pass mode, the 2-3 field pattern fixer 10 analyzes the disruptedvideo signal VIDEO_(IN) and generates, based on the results of thisanalysis, the undisrupted video signal VIDEO_(OUT) from the disruptedvideo signal VIDEO_(IN) as the analysis is being performed. The 2-3field pattern fixer 10 is configured, such that the disrupted videosignal VIDEO_(IN) is corrected in real time. In the two-pass mode, the2-3 field pattern fixer 10 analyzes several scenes of the disruptedvideo signal VIDEO_(IN), and stores the results of the analysis (firstpass). Based on the stored results of the analysis, the undisruptedvideo signal VIDEO_(OUT) is then generated from a duplicated videosignal VIDEO_(IN)′ (second pass). The 2-3 field pattern fixer 10 isconfigured, such that the disrupted video signal VIDEO_(IN) is correctedin real time during the second pass. In this connection, the 2-3 fieldpattern fixer 10 generally includes a field sequence detector 12, a timecode comparator 14, a field sequence analyzer 16, a field sequencegenerator 18, and a multiple delay tap circuit 20, the arrangement ofwhich will be described in further detail below.

The field sequence detector 12 detects the discontinuous 2-3 fieldsequence within the disrupted video signal VIDEO_(IN), which is seriallyfed into the input IN, and generates a field difference value ΔFD inresponse thereto indicative of the detected 2-3 field sequence. In thisconnection, the field sequence detector 12 includes an input 22 on whichthe disrupted video signal VIDEO_(IN) is received. The field sequencedetector 12 further includes an absolute value subtractor 24, one inputof which is directly coupled to the input 22 and the other input ofwhich is coupled to the input 22 through a two-field delay 26.Preferably, the two-field delay 26 is implemented using a random accessmemory (RAM), which can be used to respectively write the serial bits ofthe video signal to and read the serial bits of the video signal from.It should be noted however, that any circuit that generates a two-fielddelay can be employed without straying from the principles of thisinvention. The absolute value subtractor 24 subtracts the pixel valueswithin the current field from the pixel values within a field twiceremoved in sequence from the current field, and outputs an absolute,unsigned pixel difference value ΔPIX in response thereto.

The field sequence detector 12 further includes a field accumulator 28,a vertical detector 30 and a memory device 31. The field accumulator 28is coupled to the absolute value subtractor 24 and accumulates the pixeldifference values ΔPIX as they are output from the absolute valuesubtractor 24. The field accumulator 28 then generates and outputs anaccumulated pixel difference value ΔPIX_(ACC). The memory device 31 iscoupled to the field accumulator 28 and stores the accumulated pixeldifference value ΔPIX_(ACC) as it is output from the field accumulator28. The vertical detector 30 is coupled to the input 22 and detects avertical synchronization signal within the disrupted video signalVIDEO_(IN), and thus the beginning of the next field. Upon detection ofthe vertical synchronization signal, the vertical detector 30simultaneously sends a reset signal RST to the field accumulator 28 toreset the accumulated pixel difference value ΔPIX_(ACC) to 0, and a savesignal SAVE to the memory device 31 to save the accumulated pixeldifference value ΔPIX_(ACC), which is then output on an output 32 as thefield difference value ΔFD. This process is repeated for each field ofthe disrupted video signal VIDEO_(IN). As will be discussed in furtherdetail below, the field difference value ΔFD is indicative of the 2-3field sequence, namely, a phase of the 2-3 field sequence and an editpoint, i.e., a scene change, within 2-3 field sequence.

The time code comparator 14 is employed when the 2-3 field pattern fixer10 is in the second pass of the two-pass mode, and synchronizes thefields of the duplicated disrupted video signal VIDEO_(IN)′ with thecorresponding fields of the disrupted video signal VIDEO_(IN), which waspreviously analyzed during the first pass. A time code reader 15converts a vertical interval time code (VITC) incorporated within thedisrupted video signal VIDEO_(IN) into a current time code TC_(CUR) or aVITC incorporated within the duplicated disrupted video signalVIDEO_(IN) into a current time code TC_(CUR)′. The current time codesTC_(CUR) or TC_(CUR)′ are generated in the form of parallel time codedata bits. Alternatively, the time code reader 15 can convert alongitudinal time code (LTC), which is sent to the time code reader 15independently of a video signal, into the current time codes TC_(CUR) orTC_(CUR)′. The time code comparator 14 compares the current time codeTC_(CUR)′ of the duplicated disrupted video signal VIDEO_(IN)′, receivedat a first input 34, and a trigger time code TC_(TR) obtained from apreviously analyzed disrupted video signal VIDEO_(IN), received at asecond input 36, and outputs a trigger signal S_(TR) at an output 38. Inthe preferred embodiment, the trigger signal S_(TR) is a two bit signal.When the current time code TC_(CUR) matches the trigger time codeTC_(TR), the first bit of the trigger signal S_(TR) is high. When thecurrent time code TC_(CUR) is less than the trigger time code TC_(TR),the first bit of the trigger signal S_(TR) is low. When the current timecode TC_(CUR) is greater than the trigger time code TC_(TR), the secondbit of the trigger signal S_(TR) is high, indicating an error condition.The operation of the time code comparator 14 and the significance of thetrigger signal S_(TR) will be discussed in further detail below.

A time code/field difference encoder 40 is coupled to the output 32 ofthe field sequence detector 12, the output 38 of the time codecomparator 14 and the current time code TC_(CUR). The time code/fielddifference encoder 40 encodes the current time code TC_(CUR) (orTC_(CUR)′), trigger signal S_(TR), and field difference value ΔFD intoan encoded character string CDE_(ANL) for use by the field sequenceanalyzer 16. An exemplary format for the character string CDE_(ANL) is<AA:BB:CC:DD:E>GGGGGG/CR/LF/. AA:BB:CC:DD:E is encoded from the currenttime code TC_(CUR), with AA representing hours, BB representing minutes,CC representing seconds, DD representing video frame number between 0and 29, and E representing even or odd field. The “>” sign is encodedfrom the two bits of the trigger signal S_(TR), and changes to an “=”sign if the current time code TC_(CUR) equals the trigger time codeTC_(TR), or an “?” sign if the current time code TC_(CUR) is greaterthan the trigger time code TC_(TR). GGGGGG indicates the fielddifference value ΔFD. CR represents a carriage return, and LF representsline feed. The character string CDE_(ANL) is input into aFirst-In-First-Out (FIFO) memory 42, where several character stringsCDE_(ANL) can be stored. The FIFO 42 allows the field sequence analyzer16 and field sequence generator 18 to utilize the character stringsCDE_(ANL) in non-real time. This is especially important if the fieldsequence analyzer 16 and field sequence generator 18 are embodied in apersonal computer (PC), which typically does not read its serial portimmediately.

The field sequence analyzer 16 decodes and analyzes the field differencevalues ΔFD encoded in the character strings CDE_(ANL), which are used todetermine the 2-3 field sequence of the disrupted video signalVIDEO_(IN). The field sequence generator 18 generates field sequencereorganization information in the form of a field sequence correctionsignal S_(COR) and a trigger time code TC_(TR), which are encoded in acharacter string CDE_(CTRL). As will be discussed in further detailbelow, the trigger time code TC_(TR) corresponds to the particular fieldof the duplicated disrupted video signal VIDEO_(IN)′ to which the fieldsequence correction signal will be applied during the second pass in atwo-pass mode. Preferably, the field sequence analyzer 16 and fieldsequence generator 18 are embodied in a standard personal computer (PC).It should be noted, however, that the field sequence analyzer 16 andfield sequence generator 18 can be embodied in logic circuitry withoutstraying from the principles of this invention. The PC includes an RS232serial input port 44, which is coupled to the FIFO 42, and an RS232serial output port 46.

The field sequence analyzer 16 particularly analyzes the fielddifference values ΔFD to determine the phase of the discontinuous 2-3field sequence and any edit point within the 2-3 field sequence. Forinstance, FIG. 2 depicts an exemplary discontinuous 2-3 field sequencehaving alternating distinct two-field sequences 2FS and distinctthree-field sequences 3FS. The reference letters A, B, C, D, etc.,respectively designate the film frames from which the fields arederived. The reference numbers 1 and 2 respectively designate field 1and field 2 (odd and even, or even and odd). As is apparent, adiscontinuity in the form of an edit point EP (or scene change) has beengenerated between field H2 and field M1, causing, in this case, a changein the phase of the 2-3 field sequence. The field difference values ΔFDoutput from the field sequence detector 12 are indicative of the firstfield of a scene change, as well as the third field of a distinctthree-field sequence. That is, a comparison of the first two fieldsimmediately subsequent to a scene change with the first two fieldsprevious to each will result in a relatively large field differencevalue ΔFD for two fields. On the contrary, a comparison of the third andfirst fields of a distinct three-field sequence 3FS will result in arelatively low field difference value ΔFD. If the disrupted video signalVIDEO_(IN) is generated from a telecine digital recording that repeatsthe third field of the three-field frame from digital memory, the fielddifference value ΔFD may actually be zero. Comparison of a field that isnot the first field of a scene change or the third field of a distinctthree-field sequence 3FS will result in a nominal field difference valueΔFD providing a reference for determination of the first field of ascene change and the third field of a distinct three-field sequence 3FS.

FIG. 3 shows a sequence of field difference values ΔFD output from thefield sequence detector 12 as each field of the 2-3 field sequencedepicted in FIG. 2 is detected. As can be seen, a high field differencevalue ΔFD is output from the field sequence detector 12 at field 21 (M1)indicating field M1 as the first field of a scene change. A low fielddifference value ΔFD is output from the field sequence detector 12 atfields 5 (B1), 10(D2), 15(F1), 20(H2), 24(N2), 29(P1), 34(R2), 39(T1),etc., indicating the third field of each of the distinct three-fieldsequences, which repeats every five fields up until field 24(N2), andthen repeats every five fields thereafter.

The field sequence analyzer 16 analyzes the sequence of field differencevalues ΔFD to determine the first field of the scene change and thechange in the phase of the 2-3 field sequence. To determine a phasechange within the 2-3 field sequence, the field sequence analyzer 16correlates the third field of every three-field sequence 3FS to thecurrent time code TC_(CUR). The field sequence analyzer 16 firstconverts the current time code TC_(CUR) to an integer, and then performsa modulo-5 operation on this integer to obtain a repeating time codesequence of 0, 1, 2, 3, 4. The field sequence analyzer 16 thencorrelates the third field of every three-field sequence 3FS with one ofthese five integers. In a continuous 2-3 field sequence, every thirdfield of a three-field sequence 3FS will correlate with the sameinteger, indicating a constant phase through the 2-3 field sequence.When there is a discontinuity within the 2-3 field sequence (typicallycaused by an edit point), the phase of the 2-3 field sequence willusually be altered. For instance, assuming field 1 (A1) in FIG. 2correlates with the time code integer 0, the phase of the discontinuous2-3 field sequence correlates with the time code integer 4 (fields5(B1), 10(D2), 15(F1), 20(H2)) up until the edit point EP. After theedit point EP, the phase of the discontinuous 2-3 field sequencecorrelates with the time code integer 3 (fields 24(N2), 29(P1), 34(R2),39(T1)), thus representing a phase change of −1. An edit point thatoccurs immediately after the third field of a three-field sequence 3FSor the second field of a two-field sequence without a phase change willnot generate a discontinuity within the 2-3 field sequence. Thiscondition generally occurs 8% of the time. A phase change in the 2-3field sequence not resulting from an edit point EP indicates an errorcondition.

Based on the determination of the first field of the scene change andthe phase change of the discontinuous 2-3 field sequence, the fieldsequence generator 18 generates field sequence reorganizationinformation, which can subsequently be applied to either the disruptedvideo signal VIDEO_(IN) (one-pass mode) or the duplicated disruptedvideo signal VIDEO_(IN)′ (two-pass mode), to generate the undisruptedvideo signal VIDEO_(OUT). This reorganization information is based on areorganization of the disrupted 2-3 field sequence internally performedwithin the field sequence generator 18. In particular, with knowledge ofthe first field of the scene change and the phase change of thediscontinuous 2-3 field sequence obtained from the field sequenceanalyzer 16, the field sequence generator 18 deletes, repeats and/orswaps fields within the discontinuous 2-3 field sequence to generate thecontinuous 2-3 field sequence. For instance, a distinct two-fieldsequence 2FS can be changed to a distinct three-field sequence 3FS byrepeating one of the fields. A distinct three-field sequence 3FS can bechanged to a distinct two-field sequence 2FS by deleting the first orthird field of the distinct three-field sequence 3FS. A distincttwo-field sequence 2FS composed of an odd field and then an even fieldcan be changed to a distinct two-field sequence 2FS composed of an evenfield and then an odd field by swapping fields, and vice versa. Adistinct three-field sequence 3FS composed of an even field, then an oddfield, and then an even field can be changed to a distinct three-fieldsequence 3FS composed of an odd field, then an even field, and then anodd field by repeating and deleting fields.

As will be described in further detail below, the field sequencegenerator 18 performs this reorganization by associating a relativedelay for certain of the fields of the discontinuous 2-3 field sequence.This delay information is used to generate a delay sequence for each ofthe fields of the continuous 2-3 field sequence, beginning with thefirst field of the scene and ending with the last field of the scene(the scene change location may move a field or two after this process).For instance, the discontinuous 2-3 field sequence of FIG. 2 is shownreconstructed into either a first continuous 2-3 field sequence or asecond continuous 2-3 field sequence by assuming a relative delay forcertain of the fields of the discontinuous 2-3 field sequence. As isapparent, frame 21(M1) is the first field of the scene change, and thescene change has caused a phase change in the 2-3 field sequence of −1(i.e., frame 24(N2) is four frames removed from frame 20(D2) instead offive). Based on this, the field sequence generator 18 can determine forcertain fields, the delay required to generate a continuous 2-3 fieldsequence.

For instance, to construct the first continuous 2-3 field sequence, thefield sequence generator 18 derives the partial field sequenceM1/M2/N1/N2/N1 from the discontinuous 2-3 field sequence by associatinga 0 field delay and a 1 field delay with field 21(M1), a 0 field delayand a 2 field delay with field 23(N1), and a 0 field delay with field24(N2). The field sequence M1/M2/N1/N2/N1 can then be respectively usedfor fields 21-25. It should be noted that only the fields of thediscontinuous 2-3 field sequence required to construct a continuous 2-3field sequence have a delay associated therewith. For example, a delayis not associated with field 22(N2), which is effectively ignored.Carrying this process throughout the scene will result in a delaysequence of 0, 1, 0, 0, 2, 0, 2, 0, 0, 2, 0, 2 for fields 21-32. As canbe seen, a repeating delay sequence of 0,0,2,0,2 occurs after the 1field delay. Although not depicted, odd field delays can occur at theend of the scene, just like at the beginning of the scene.

To construct the second 2-3 field sequence, the field sequence generator18 derives the sequence N1/N2/O1/O2/O1 from the discontinuous 2-3 fieldsequence by associating a −2 field delay with field 23(N1), a 0 fielddelay with field 22(N2), a −2 field delay and a 0 field delay with field25(01), and a −2 field delay for field 26(02). A delay is not associatedwith frame 21(M1) and frame 24(N2), which are effectively ignored. Thus,a delay sequence having a repeating delay sequence of −2,0,−2,−2,0, isgenerated for fields 21-25, and so on. It should be noted that, inreality, a negative delay cannot be achieved. The negative delaysrepresented in FIG. 2, however, are relative to a fixed delay. Forexample, if there is a fixed delay of 10 fields, a −2 field delay wouldactually be an absolute 8 field delay. As will be discussed in furtherdetail below, the field sequence generator 18 generates a delay sequencebased on various criteria.

The delay sequence is used to generate a correction signal S_(COR). Whenthe 2-3 pattern fixer 10 is in the two-pass mode, the field sequencecorrection signal S_(COR) along with the corresponding time code, i.e.,the trigger time code TC_(TR) is stored in a log 48 during the firstpass of the two-pass mode. For example, the delay sequence 0, 1,0,0,2,0,2, 0,0,2,0,2, etc. depicted in FIG. 2 with respect to the firstcontinuous 2-3 field sequence will result in a correction signal of 0, 1and a correction signal of 0, 0, 2, 0, 2. The repeating delay sequenceof −2,0,−2,−2,0 depicted in FIG. 2 with respect to the second continuous2-3 field sequence will result in a single correction signal of −2, 0,−2, −2, 0. A multitude of correction signals S_(COR) and correspondingtrigger time codes TC_(TR) are accumulated over several scenes andstored in the log 48.

The field sequence correction signals S_(COR) and corresponding triggertime codes TC_(TR) are encoded into control character strings CDE_(CTRL)and output on the RS232 serial output port 46. An exemplary format forthe character string CDE_(CTRL) is {AA:BB:CC:DD:E}HHHHH/CR/LF/, whereAA:BB:CC:DD:E is the trigger time code TC_(TR) with AA representinghours, BB representing minutes, CC representing seconds, DD representingvideo frame number between 0 and 29, and E representing even or oddfield; HHHHH represents the field sequence correction signal S_(COR) ;CR represents carriage return; and LF represents line feed. Thecharacter string CDE_(CTRL) is input into a First-In-First-Out (FIFO)memory 50, where several character strings CDE_(CTRL) can be stored. TheFIFO 50 obviates the need for the field sequence analyzer 16 and fieldsequence generator 18 to respond to each field, eliminating the need ofthe field sequence analyzer 16 and field sequence generator 18, i.e.,the PC, to operate in real time. The output of the time code comparator14 is coupled to and inputs the trigger signal S_(TR) into the FIFO 50.When the 2-3 field pattern fixer 10 is performing the second pass of thetwo-pass mode, and when the trigger signal S_(TR) indicates that thecurrent time code TC_(CUR) is equal to the trigger time code TC_(TR) asdiscussed above, the FIFO 50 outputs the next control character stringCDE_(CTRL). When the 2-3 field pattern fixer 10 is in the one-pass mode,the field sequence generator 18 provides the signal to output thecontrol character string CDE_(CTRL).

A time code/correction signal decoder 52 is coupled to the FIFO 50 andreceives the next control character string CDE_(CTRL). The timecode/correction signal decoder 52 outputs, on a first output, thedecoded correction signal S_(COR) for subsequent use by the multipledelay tap circuit 20 and on a second output, the trigger time codeTC_(TR) for input into the second input 36 of the time code comparator14. As will be described in further detail below, application of thetrigger time code TC_(TR) to the second input 36 of the time codecomparator 36 and subsequent generation of the trigger signal S_(TR)allows the proper correction signal S_(COR) to be applied to theduplicated disrupted video signal VIDEO_(IN)′ when the 2-3 pattern fixer10 is in the two-pass mode.

The field sequence analyzer 16 generates a reset code CDE_(RST) if thecurrent time code TC_(CUR) backs up, i.e., the videotape is rewound. Thereset code CDE_(RST) is output when the current time code TC_(CUR)either stops or is forwarded, i.e., the videotape is cued or played. Thereset decoder 54 is coupled to the field sequence analyzer 16 anddecodes the reset code CDE_(RST) upon reset thereof. The output of thereset decoder 54 is coupled to and clears the FIFO 50 and timecode/correction signal decoder 52 in response to the reset codeCDE_(RST). The reset code CDE_(RST) allows the field sequence analyzer16 to clear the control character strings CDE_(CTRL) from the FIFO 50and input the proper control character strings CDE_(CTRL) when thecleared control character strings CDE_(CTRL) are out of synchronizationwith the current time code TC_(CUR).

The multiple delay tap circuit 20 includes a first input 55 to receivethe disrupted video signal VIDEO_(IN) (or duplicated video signalVIDEO_(IN)′) and an output 56 to output the undisrupted video signalVIDEO_(OUT). A second input 58 of the multiple delay tap circuit 20 iscoupled to the output of the time code/correction signal decoder 52 toreceive the field sequence correction signal S_(COR). The multiple delaytap circuit 20 includes a fixed delay 60, a bank of delay taps 62 and adelay tap selector 64. For the purposes of illustration, the bank ofdelay taps 62 is shown to include 0, 1, 2, 3, and 4 field delay taps.Each of the fields of the disrupted video signal VIDEO_(IN) orduplicated video signal VIDEO_(IN)′ can be relatively delayed within arange of between −2 and 2 fields, as discussed above. Preferably, thefixed delay 60 is several fields in length to provide the field sequenceanalyzer 16 enough time to analyze the discontinuous 2-3 field sequenceof the disrupted video signal VIDEO_(IN) and the field sequencegenerator 18 enough time to generate the field sequence correctionsignals S_(COR) in response thereto, when the 2-3 field pattern fixer 10is in the one-pass mode. Preferably, the fixed delay 60 and delay taps62 are implemented using a random access memory (RAM). It should benoted that the audio signal (not shown) should be delayed the samenumber of fields equal to the fixed delay 60 plus the delay of thecenter tap to facilitate the synchronization of the audio signal and theundisrupted video signal VIDEO_(OUT) when applied to videotape.

The bank of field delay taps 62 include delay taps 0, 1, 2, 3, and 4,which represent alternating even and odd fields of delay, i.e., relativedelays of −2, −1, 0, 1, and 2 fields. Delay tap 0 (relative delay of −2fields) is generated by connecting a direct line between the fixed delay60 and the delay control circuit 88. Delay tap 1 (relative delay of −1field) is generated by connecting a 262½-line delay between the fixeddelay 60 and the delay control circuit 88. The 262½-line delay iscreated by averaging, through an averaging circuit 70, a 262-line delay66 with the 262-line delay 66 in series with a 1-line delay 68. Delaytap 2 (relative delay of 0 fields) is generated by connecting a 525-linedelay 72 between the fixed delay 60 and the delay control circuit 88.Delay tap 3 (relative delay of 1 field) is generated by connecting the525-line delay 72 and 262½-line delay between the fixed delay 60 and thedelay control circuit 88. The 262½-line delay is created by averaging,through an averaging circuit 78, a 262-line delay 74 with the 262-linedelay 74 in series with a 1-line delay 76. Delay tap 4 (relative delayof 2 fields) is generated by connecting the 525-line delay 72 and a525-line delay 80 between the fixed delay 60 and the delay controlcircuit 88. It should be noted that by adjusting the number of lines ineach delay appropriately, the 2-3 pattern fixer 10 can be used for otherapplications, such as, e.g., high definition television (HDTV).

The delay tap selector 64 includes a register 82, a switch 84, a counter86 and a delay control circuit 88. The register 82 is connected to thesecond input 58 and stores the field sequence correction signal S_(COR)received on the second input 58 from the time code/correction signaldecoder 52. The delay numbers within the field sequence correctionsignal S_(COR) are respectively output onto five lines leading to fivetakeoffs on the switch 84. The counter 86, which continuously countsfrom 1 to 5, is operatively coupled to the switch 84, such that theswitch 84 serially outputs the delay numbers of the field sequencecorrection signal S_(COR). The register 82 and counter 86 each includesan input coupled to the output 38 of the time code comparator 14 toreceive the trigger signal S_(TR). When the trigger signal S_(TR)indicates that the current time code TC_(CUR) equals the trigger timecode TC_(TR), the register 82 saves the field sequence correction signalS_(COR) output from the time code/correction signal decoder 52 and thecounter 86 is reset to 1. The counter 86 is keyed to the beginning ofeach field. In this regard, the output of the vertical detector 30 iscoupled to the counter and sends an advance signal ADV thereto at thebeginning of each field. In this manner, a delay number is output fromthe switch 84 at the beginning of each field. The delay control circuit88 is coupled between the switch 84 and the bank of delay taps 62. Thedelay control circuit 88 selects a particular tap corresponding to thedelay number received by the delay control circuit 88. For instance, ifthe delay number received by the delay control circuit 88 is −2, thedelay control circuit 88 will select delay tap 0. By selecting theappropriate delay taps, the disrupted video signal VIDEO_(IN) (orduplicated disrupted video signal VIDEO_(IN)′) received at the firstinput 55 of the multiple delay tap circuit 20 can be reconstructed togenerate the undisrupted video signal VIDEO_(OUT) at the output 56 ofthe multiple delay tap circuit 20 in accordance with the field sequencecorrection signal S_(COR) generated by the field sequence generator 18.It should be noted that the bank of delay taps 62 can include more delaytaps than those depicted in FIG. 1, providing the field sequencegenerator 18 increased flexibility in selecting a delay sequence.

It should be noted that a vertically blurred field is generated when theodd field delay taps (1-field and 3-field delay taps) are used due tothe averaging of signals offset from each other by a 1-line delay. Assuch, it is generally undesirable to generate a delay sequence with anodd number. This undesirable effect, however, will only occur in aminimum number of fields, generally at the beginning and/or the end of ascene.

The resultant blurred field may be minimized or eliminated by derivingat least a portion of the field from a field that is delayed an evennumber of fields, by employing the multiple delay tap circuit 100depicted in FIG. 4, instead of the multiple delay tap circuit 20depicted in FIG. 1. The multiple delay tap circuit 100 includes acompensating bank of delay taps 102, along with the fixed delay 60 andthe delay tap selector 64. As with the bank of delay taps 62, delay taps0, 2 and 4 represent even fields of delay (i.e., relative delays of −2,0 and 2 fields). Delay tap 0 (relative delay of −2 fields) is generatedby connecting a 525-line delay 106 between the fixed delay 60 and thedelay control circuit 88. Delay tap 2 (relative delay of 0 fields) isgenerated by connecting the 525-line delay 106 and a 525-line delay 110between the fixed delay 60 and the delay control circuit 88. Delay tap 4is generated by connecting the 525-line delays 106 and 110 and a525-line delay 114 between the fixed delay 60 and the delay controlcircuit 88.

The bank of delay taps 102 are compensating in that delay tap 1 can becross-faded between a first odd-delayed field, i.e., field with arelative delay of −1 field (−1FD), and one of the two even-delayedfields immediately adjacent the first odd-delayed field, i.e., a fieldwith a relative delay of −2 fields or 0 fields (−2FD or 0FD); and delaytap 3 can be cross-faded between a second odd-delayed field, i.e., afield having a relative delay of 1 field (1FD), and one of the twoeven-delayed fields immediately adjacent the second odd-delayed field,i.e., a field having a relative delay of 0 fields or 2 fields (0FD or2FD). In particular, as the difference in the pixel difference valuesΔPIX between an odd-delayed field and one of the immediately adjacentodd-delayed fields increases, indicating increased motion, the delaytaps 1 and 3 are faded to an odd field delay. On the contrary, as thedifference in the pixel difference values ΔPIX between an odd-delayedfield and one of the immediately adjacent odd-delayed fields decreases,indicating decreased motion, the delay taps 1 and 3 are faded to one ofthe immediately adjacent even-delayed fields. To ensure that there iscross-fading between an odd-delayed field and an even-delayed fieldwithin the same scene, the lesser of the two even field delays (−2FD)immediately adjacent the first odd-delayed field (−1FD), and the lesserof the two even field delays (0FD) immediately adjacent the secondodd-delayed field (1FD) are selected at the beginning of the scene, andthe greater of the two even field delays (0FD) immediately adjacent thefirst odd-delayed field (−1FD) and the greater of the two even fielddelays (2FD) immediately adjacent the second odd-delayed field (1FD) areselected at the end of the scene.

Cross-fading between the first odd-delayed field (−1FD) and one of thetwo immediately adjacent even-delayed fields (−2FD or 0FD) isaccomplished through a first cross-fader 126 and associated first switch130. In particular, the 525-line delay 106 and a 262½-line delay areconnected between the fixed delay 60 and a first input of the firstcross-fader 126. The 262½-line delay is created by averaging, through anaveraging circuit 118, a 262-line delay 108 with the 262-line delay 108in series with a 1-line delay 120. The 525-line delay 106 and the525-line delay 106 in series with a 525-line delay 110 are connectedbetween the fixed delay 60 and a second input of the first cross-fader126 via the first switch 130.

Similarly, cross-fading between the second odd-delayed field (1FD) andone of the two immediately adjacent even fields (0FD or 2FD) isaccomplished through a second cross-fader 128 and associated secondswitch 132. In particular, the 525-line delays 106 and 110 and a262½-line delay are connected between the fixed delay 60 and a firstinput of the second cross-fader 128. The 262½-line delay is created byaveraging, through an averaging circuit 122, a 262-line delay 112 withthe 262-line delay 112 in series with a 1-line delay 124. The 525-linedelays 106 and 110, and the 525-line delays 106 and 110 in series with a525-line delay 114 are connected between the fixed delay 60 and anotherinput of the second cross-fader 128 via the second switch 132.

A switch signal SWITCH, preferably generated in the field sequenceanalyzer 16, is applied to the first switch 130 to toggle selectionbetween one of the two even field delays (−2FD or 0FD) immediatelyadjacent the first odd-delayed field (−1FD). The same switch signalSWITCH is applied to the second switch 132 to toggle selection betweenone of the two even field delays (0FD or 2FD) immediately adjacent thesecond odd-delayed field (1FD). Thus, application of the switch signalSWITCH to the respective first and second switches 130 and 132 eitheroutputs the lesser of the even field delays (−2FD and 0FD) to therespective first and second cross-faders 126 and 128, preferably at thebeginning of the scene, or the greater of the even field delays (0FD and2FD) to the respective first and second cross-faders 126 and 128,preferably at the end of the scene. As will be described in furtherdetail below, application of the first control signal CTRL1 to the firstcross-fader 126 cross-fades between the first odd-delayed field (−1FD)and the selected immediately adjacent even field (−2FD or 0FD).Similarly, application of the second control signal CTRL2 to the secondcross-fader 128 cross-fades between the second odd-delayed field (1FD)and the selected immediately adjacent even field (0FD or 2FD).

The first control signal CTRL1 is generated thusly. A first input of afirst absolute value subtractor 138 is coupled to the 262-line delay 108and a second input of the first absolute value subtractor 138 is coupledto the output of a third switch 134. A first input of the third switch134 is coupled to the 262-line delay 104 and a second input of the thirdswitch 134 is coupled to the 262-line delay 112. Thus, the firstabsolute value subtractor 138 compares, on a pixel-by-pixel basis, thefirst odd-delayed field (−1FD) with one of the fields having an oddfield delay (−3FD or 1FD) immediately adjacent the first odd-delayedfield (−1FD). The switch signal SWITCH is applied to the third switch134 to select between the two immediately adjacent odd-delayed fields(−3FD or 1FD). That is, at the beginning of the scene, the lesserimmediately adjacent odd-delayed field (−3FD) immediately adjacent thefirst odd-delayed field (−1FD) is selected. At the end of the scene, thegreater immediately adjacent odd-delayed field (1FD) is selected. Thefirst absolute value subtractor 138 calculates the absolute differencebetween the pixels of the first odd-delayed field (−1FD) and theselected immediately adjacent odd-delayed field (−3FD or 1FD), andgenerates an absolute pixel difference ΔPIX value in response thereto .Because the determination of the motion within the immediately adjacenteven-delayed field (−2FD or 0FD) is pertinent to whether the firstcross-fader 126 fades to the selected immediately adjacent even-delayedfield (−2FD or 0FD), the absolute pixel difference value ΔPIX ispreferably further processed to provide a more accurate estimate of themotion within the selected immediately adjacent even-delayed field (−2FDor 0FD). Thus, a first input of a first fade control 140 is directlycoupled to the output of the first absolute value subtractor 138, and asecond input of the first fade control 140 is coupled to the output ofthe absolute value subtractor 138 via a 1-line delay 142.

The first fade control 140 averages, or alternatively, adds the absolutepixel difference value ΔPIX with the absolute pixel difference valueΔPIX delayed by 1-line. Alternatively, the fade control 140 selects themaximum of the absolute pixel difference value ΔPIX and the absolutepixel difference value ΔPIX delayed by 1-line, so that the firstcross-fader 126 conservatively fades to the selected immediatelyadjacent even field delay (−2FD or 0FD). The fade control 140 generatesthe first control signal CTRL1, which is input into the firstcross-fader 126. As the amplitude of the first control signal CTRL1decreases, the further the first cross-fader 126 fades to the selectedimmediately adjacent even-delayed field (−2FD or 0FD), and as theamplitude of the first control signal CTRL1 increases, the further thefirst cross-fader 126 fades to the first odd-delayed field (−1FD).

The second control signal CTRL2 is generated thusly. A first input of asecond absolute value subtractor 144 is coupled to the 262-line delay112 and a second input of the second absolute value subtractor 144 iscoupled to the output of a fourth switch 136. A first input of thefourth switch 136 is coupled to the 262-line delay 108 and a secondinput of the fourth switch 136 is coupled to a 262-line delay 116. Thus,the second absolute value subtractor 144 compares, on a pixel-by-pixelbasis, the second odd-delayed field (1FD) with one of the odd-delayedfields (−1FD or 3FD) immediately adjacent the second odd-delayed field(1FD). The switch signal SWITCH is applied to the fourth switch 136 toselect between the two immediately adjacent odd-delayed fields (−1FD or3FD). That is, at the beginning of the scene, the lesser delayedimmediately adjacent odd field (−1FD) is selected, and at the end of thescene, the greater immediately adjacent odd-delayed field (3FD) isselected. The second absolute value subtractor 144 calculates theabsolute difference between the pixels of the second odd-delayed field(1FD) and the selected immediately adjacent odd field (−3FD or 1FD), andgenerates an absolute pixel difference ΔPIX value in response thereto.Because the determination of the motion within the immediately adjacenteven-delayed field (0FD or 2FD) is pertinent to whether the secondcross-fader 128 fades to the selected immediately adjacent even-delayedfield (0FD or 2FD), the absolute pixel difference value ΔPIX ispreferably further processed to provide a more accurate estimate of themotion within the selected immediately adjacent even-delayed field (0FDor 2FD). Thus, a first input of a second fade control 146 is directlycoupled to the output of the second absolute value subtractor 144, and asecond input of the second fade control 146 is coupled to the output ofthe second absolute value subtractor 144 via a 1-line delay 148.

The second fade control 146 averages, or alternatively, adds theabsolute pixel difference value ΔPIX with the absolute pixel differencevalue ΔPIX delayed by 1-line. Alternatively, the second fade control 146selects the maximum of the absolute pixel difference value ΔPIX and theabsolute pixel difference value ΔPIX delayed by 1-line, so that thefirst cross-fader 126 conservatively fades to the selected immediatelyadjacent even-delayed field (−0FD or 2FD). The second fade control 146generates the second control signal CTRL2, which is input into thesecond cross-fader 128. As the amplitude of the second control signalCTRL2 decreases, the further the second cross-fader 128 fades to theselected immediately adjacent even-delayed field (0FD or 2FD), and asthe amplitude of the second control signal CTRL2 increases, the furtherthe second cross-fader 128 fades to the second odd-delayed field (1FD).

The 2-3 field pattern fixer 10 can be selectively operated in theone-pass mode or the two-pass mode. Operation of the 2-3 field patternfixer 10 in the two-pass mode is described as follows. During the firstpass, the disrupted video signal VIDEO_(IN) is serially received at theinput 22 of the field sequence detector 12 where the fields of thediscontinuous 2-3 field sequence are sequentially detected and comparedto the fields two fields previous. The field sequence detector 12generates and outputs field difference values ΔFD at the output 32 inresponse to these comparisons. The time code/field difference encoder 40encodes the current time codes TC_(CUR) and the corresponding fielddifference values ΔFD into a series of character strings CDE_(ANL),which are stored in the FIFO 42 for subsequent analysis by the fieldsequence analyzer 16. During the first pass, the trigger signals S_(TR)are either not encoded into the character strings CDE_(ANL) or ignoredby the field sequence analyzer 16.

The field sequence analyzer 16 receives the series of character stringsCDE_(ANL) at the input port 44, and then decodes and analyzes the seriesof field difference values ΔFD to determine a discontinuity of thediscontinuous 2-3 field sequence, and in particular, the first field ofthe scene change and phase change of the discontinuous 2-3 fieldsequence. Because the undisrupted video signal VIDEO_(OUT) is notgenerated until the second pass in the two-pass mode, the field sequenceanalyzer 16 can analyze the entire scene to facilitate the determinationof the first field of the scene change and the phase change of thediscontinuous 2-3 -field sequence. This capability becomes significantwhen the beginning of the scene has no or very little motion making itsometimes difficult to distinguish between a third field of a distinctthree-field sequence 3FS and the other fields until later in the scene.Thus, although the beginning of the scene may not be determined untilmuch later in the scene, the second pass allows the correction signalS_(COR) to be timely applied to the duplicated disrupted video signalVIDEO_(IN) at the beginning of the scene. The field sequence generator18 then generates reorganization information in response to thisinformation. In particular, the field sequence generator 18 generatesthe field sequence correction signal S_(COR) and the correspondingtrigger time code TC_(TR). This information is logged into the log 48.Several scenes can be analyzed, and thus, several correction signalsS_(COR) and corresponding trigger time codes TC_(TR) can be logged intothe log prior to the second pass.

The reorganization of the fields of the discontinuous 2-3 field sequenceinto the fields of the continuous field sequence typically results incontinuous 2-3 field sequence that is distorted in time, causing theresulting video signal and the corresponding audio signal, which is notdistorted in time, to be out of synchronization. This will typically notcreate a problem when the respective video and audio signals areunsynchronized by a minimal amount of fields, which may result from adelay through a single scene change. For example, edit point EP depictedin FIG. 2 causes a 1 field delay for the film frames represented in thefirst continuous 2-3 field sequence (e.g., the partial sequence O2/O1 inthe first continuous 2-3 field sequence is one field delayed from thepartial sequence O1/O2 in the discontinuous 2-3 field sequence) and a−1½ field delay for the film frames represented in the second continuous2-3 field sequence (e.g., the partial sequence O1/O2/O1 in the secondcontinuous 2-3 field sequence is −1½ field delayed from the partialsequence O1/O2 in the discontinuous 2-3 field sequence).

These delays are relatively minimal. If left unchecked, however, thecumulative field delay through a series of scene changes could berelatively great, resulting in the de-synchronization of the respectivevideo and audio signals. As such, for each scene change, the fieldsequence generator 18 selects a particular delay sequence that wouldminimize the cumulative field delay, or at least maintain the cumulativefield delay within a certain range. Typically, this delay range willinclude values of −2, −1½, −1, −½, 0, +½, +1, +1½, +2. The delay range,however, can be greater or less, depending on the tolerance of the delaybetween the respective video and audio signals

Also, in selecting particular delay sequences, the field sequencegenerator 18 preferably discards disjoined single field frames, suchthat the resulting delay sequence does not include an odd field delay.For example, the M1 field depicted in FIG. 2 is discarded in generatingthe second continuous 2-3 field sequence. Thus, in selecting particularfield delay sequences, the field sequence generator 18 attempts tomaintain the cumulative field delay within a defined range, whilediscarding as many disjoined single field frames as possible. In thetwo-pass mode, several scenes can be analyzed at a time, therebyallowing a more efficient selection of the delay sequences. In theone-pass mode, the field sequence generator 18 must determine the delaysequence as each scene is analyzed, and therefore must determine whethera disjoined single field frame should be discarded based on thecumulative field delay at that point. Preferably, while in the one-passmode, the cumulative field delay is maintained on the positive side ofthe range to allow the field sequence generator 18 more flexibility indiscarding single field frames. Of course, under certain circumstances,whether in the two-pass mode or the one-pass mode, the cumulative fielddelay becomes too negative if every disjoined single field frame isdiscarded.

For example, if the cumulative field delay is negative, such as, e.g.,−2 fields, and the tolerance level of the delay between the respectivevideo and audio signals is low, the field sequence generator 18 mayselect the delay sequence used to generate the first continuous 2-3field sequence in FIG. 2, so that the absolute cumulative field delay islessened by 1 field. Although this results in the blurring of the M2field, selection of the delay sequence used to generate the secondcontinuous 2-3 field sequence would have increased the absolutecumulative field delay by 1½ fields to a cumulative total of −3½ fields,which may produce a result more undesirable than that produced byselection of the delay sequence used to generate the first continuous2-3 field sequence.

Thus, under certain circumstances, the field sequence generator 18 mustselect between which of the disjoined single field frames to discard.This selection process is preferably based on detected motion betweenthe disjoined single field frame and the immediately adjacent frame(subsequent frame if at the beginning of the scene, and preceding frameif at the end of the scene), which can be obtained from the fielddifference values ΔFD analyzed by the field sequence analyzer 16. In thecase where the basic bank of delay taps 62 is employed, the disjoinedsingle field frames in which there is detected relatively little motionare preferably discarded before those in which there is detectedrelatively great motion. This is because the vertical blurring will notbe as noticeable to the viewer when there is a lot of motion in thevertically blurred frame. In the case where the compensating bank ofdelay taps 102 is employed, the disjoined single field frames in whichthere is detected relatively great motion are preferably discardedbefore those in which there is detected relatively great motion. This isbecause the compensating bank of delay taps 102 cannot compensate forvertically blurred frames that have relatively a large amount of motion.

During the second pass, a duplicated disrupted video signal VIDEO_(IN)′is received at the first input 55 of the multiple delay tap circuit 20.At the same time or prior thereto, the field sequence generator 18encodes the multitude of correction signals S_(COR) and correspondingtrigger time codes TC_(TR) received from the log 48 into a correspondingmultitude of control character strings CDE_(CTRL). These controlcharacter strings CDE_(CTRL) are then output at the output port 46 intothe FIFO 50. The first control character string CDE_(CTRL) is advancedinto and decoded by the time code/correction signal decoder 52, whichthen transmits the field sequence correction signal S_(COR) to the delaytap selector 64 and the trigger time code TC_(TR) to the second input 36of the time code comparator 14. The current time code TC_(CUR)′ of theduplicated disrupted video signal VIDEO_(IN)′ is input into the firstinput 34 of the time code comparator 14. The current time code TC_(CUR)′and the trigger signals S_(TR) are encoded by the time code/fielddifference encoder 40 into a series of character strings CDE_(ANL) foruse by the PC to provide the user status. During the second pass, fielddifference values ΔFD are either not encoded into the character stringsCDE_(ANL) or ignored by the field sequence analyzer 16.

The field sequence correction signal S_(COR) is not applied to theduplicated disrupted video signal VIDEO_(IN)′ until the current timecode TC_(CUR)′ of the duplicated disrupted video signal VIDEO_(IN)′matches the trigger time code TC_(TR). In this connection, the time codecomparator 14 compares the current time code TC_(CUR)′ to the triggertime code TC_(TR) and generates the trigger signal S_(TR) in responsethereto. The trigger signal S_(TR) is input into the FIFO 50 and theregister 82 and counter 86 of the multiple delay tap circuit 20. If thecurrent time code TC_(CUR)′ is less than the trigger time code TC_(TR),the first bit of the two bit trigger signal S_(TR) is low. In this case,the FIFO 50 is not advanced, the register does not save the fieldsequence correction signal S_(COR), and the counter is not reset to “1”.

If the current time code TC_(CUR)′ is equal to the trigger time codeTC_(TR), the first bit of the two bit trigger signal S_(TR) is high. Inthis case, the register 82 of the multiple delay tap circuit 20 savesthe field sequence correction signal S_(COR), and the counter 86 isreset to “1”. The field sequence correction signal S_(COR) is outputfrom the register 82 to the switch 84. With the counter 86 set at “1”,the first delay number is sent to the delay control circuit 88, whichselects the delay tap within the bank of delay taps 62 in accordancewith the delay number. The FIFO 50 is advanced, transmitting the nextcontrol character string CDE_(CTRL) to the time code/correction signaldecoder 52, which decodes and transmits the next field sequencecorrection signal S_(COR) to the multiple delay tap circuit 20 and thenext trigger time code TC_(TR) to the second input 36 of the time codecomparator 14.

Until the current time code TC_(CUR) matches the next trigger time codeTC_(TR), the current field sequence correction signal S_(COR) is appliedto the duplicated disrupted video signal VIDEO_(IN)′, with the counter86 counting from 1 to 5. In this manner, the delay numbers of thecurrent field sequence correction signal S_(COR) are sequentially sentto the delay control circuit 88, thereby sequentially delaying theselected fields of the duplicated disrupted video signal VIDEO_(IN)′ togenerate the undisrupted video signal VIDEO_(OUT) at the output 56.Thus, the correction signal S_(COR) is applied to the duplicateddisrupted video signal VIDEO_(IN)′ in real time, i.e., at a field rateequal to the field rate of the disrupted video signal VIDEO_(IN).

Application of the delay numbers −2, −1, 0, 1 and 2 to the delay controlcircuit 88 prompts respective selection of the corresponding delay taps0, 1, 2, 3 and 4, and thus selection of a distinct field of theduplicated disrupted video signal VIDEO_(IN)′ that has a delaycorresponding to the current delay number. If the compensating bank ofdelay taps 102 depicted in FIG. 4 are used, selection of the fields ofthe duplicated disrupted video signal VIDEO_(IN)′ that have been delayedan odd number of fields are not distinct, but are rather cross-fadedwith an immediately adjacent field. In particular, application of an odddelay number to the delay control circuit 88 prompts selection of thecorresponding odd delay tap, and thus selection of the correspondingodd-delayed field and one of the immediately adjacent even-delayedfields. At the same time that the odd delay number is applied to thedelay control circuit 88, the switch signal SWITCH is sent from thefield sequence analyzer 16 to the first, second, third and fourthswitches 130, 132, 134 and 136 to select the particular even-delayedfield to and from which the odd-delayed field is cross-faded. Thus, ifat the beginning of the scene, the switch signal SWITCH causes theswitches 130, 132, 134 and 136 to switch down to select the greater ofthe immediately adjacent even-delayed fields (0FD and 2FD). If at theend of the scene, the switch signal SWITCH causes the switches 130, 132,134 and 136 to switch up to select the lesser of the immediatelyadjacent even-delayed fields (−2FD and 0FD).

For instance, if delay tap 1 is selected and the switches 130 and 134are switched down, the first odd-delayed field (−1FD) and the greaterimmediately adjacent even field delay (0FD) are cross-faded. The firstabsolute value subtractor 138 compares the pixels of the firstodd-delayed field (−1FD) with the pixels of the greater immediatelyadjacent odd-delayed field (1FD), generating the pixel difference valueΔPIX. The pixel difference value ΔPIX is processed through the firstfade control 140, generating the first control signal CTRL1, which isapplied to the first cross-fader 126. The first cross-fader 126 thencross-fades between the first odd-delayed field (−1FD) and the greaterimmediately adjacent even-delayed field (0FD) in accordance with thefirst control signal CTRL1. If the switches 130 and 134 are switched up,the first odd-delayed field (−1FD) and the lesser immediately adjacenteven-delayed field (−2FD) are cross-faded. The first absolute valuesubtractor 138 compares the pixels of the first odd-delayed field (−1FD)with the pixels of the lesser immediately adjacent odd-delayed field(−3FD), generating the pixel difference value ΔPIX. The pixel differencevalue ΔPIX is processed through the first fade control 140, generatingthe first control signal CTRL1, which is applied to the firstcross-fader 126. The first cross fader 126 then cross-fades between thefirst odd-delayed field (−1FD) and the lesser immediately adjacenteven-delayed field (−2FD) in accordance with the first control signalCTRL1.

In a similar manner, if delay tap 3 is selected and the switches 132 and136 are switched down, the second odd-delayed field (1FD) and thegreater immediately adjacent even-delayed field (2FD) are cross-faded.If the switches 132 and 136 are switched up, the second odd-delayedfield (1FD) and the lesser immediately adjacent even-delayed field (0FD)are cross-faded.

Referring back to FIG. 1, when the current time code TC_(CUR) does matchthe next trigger time code TC_(TR), the first bit of the two bit triggersignal S_(TR) again is high, thereby saving the next field sequencecorrection signal S_(COR) in the register 82 and clearing the counter 86to apply the next field sequence correction signal S_(COR) to theduplicated disrupted video signal VIDEO_(IN)′. The FIFO 50 is advancedto input the next control character string CDE_(CTRL) into the timecode/correction signal decoder 52 for transmission of the next fieldsequence correction signal S_(COR) to the multiple delay tap circuit 20and next trigger time code TC_(TR) to the time code comparator 14. Thisprocess is repeated until the last field sequence correction signalS_(COR) has been applied to the duplicated disrupted video signalVIDEO_(IN)′.

Operation of the 2-3 field pattern fixer 10 in the one-pass mode isdescribed as follows. The disrupted video signal VIDEO_(IN) is seriallyreceived at the input 22 of the field sequence detector 12 and the firstinput 55 of the multiple delay tap circuit 20. The field sequencedetector 12 sequentially detects the fields of the discontinuous 2-3field sequence and compares these fields to the fields two fieldsprevious. The field sequence detector 12 generates and outputs fielddifference values ΔFD at the output 32 in response to these comparisons.The time code/field difference encoder 40 encodes the current time codesTC_(CUR), the corresponding field difference values ΔFD, and the triggersignals S_(TR) from the time code comparator 14 into a series ofcharacter strings CDE_(ANL), which are stored in the FIFO 42 forsubsequent analysis by the field sequence analyzer 16. When the 2-3field pattern fixer 10 is in the one-pass mode, the trigger signalsS_(TR) are either not encoded in the character strings CDE_(ANL) or areignored by the field sequence analyzer 16.

The field sequence analyzer 16 receives the series of character stringsCDE_(ANL) at the input port 44, and then decodes and analyzes the seriesof field difference values ΔFD to determine a discontinuity of thediscontinuous 2-3 field sequence, and in particular, the first field ofthe scene change and phase change of the discontinuous 2-3 fieldsequence. The field sequence generator 18 then generates reorganizationinformation in response to this information. In particular, the fieldsequence generator 18 generates the field sequence correction signalS_(COR). A corresponding trigger time code TC_(TR) is not generated,since the field sequence correction signal S_(COR) must be applied tothe disrupted video signal VIDEO_(IN) as it is generated. The fixeddelay 60 in the multiple delay tap circuit 20 is long enough to allowthe sequence analyzer 16 and field sequence generator 18 to analyze theseries of field difference values ΔFD and generate the field sequencecorrection signal S_(COR) in time to apply the field sequence correctionsignal S_(COR) to the selected fields of the disrupted video signalVIDEO_(IN). If the disrupted video signal VIDEO_(IN) originates from adigital recording, the identity or near identity of the first and thirdfields of each distinct three-field sequence 3FS should allow the fieldsequence analyzer 16 to determine the discontinuity of the discontinuous2-3 field sequence quickly, even if there is no or very little motionwithin the scene.

The field sequence generator 18 encodes the field sequence correctionsignal S_(COR) into a control character string CDE_(CTRL), which is thenoutput at the output port 46 into the FIFO 50. The control characterstring CDE_(CTRL) is advanced into and decoded by the timecode/correction signal decoder 52, which then transmits the fieldsequence correction signal S_(COR) to the multiple delay tap circuit 20,where it is applied to the disrupted video signal VIDEO_(IN). In thisconnection, the register 82 of the multiple delay tap circuit 20 savesthe field sequence correction signal S_(COR), and the counter 86 isreset to “1” upon the receipt of a trigger signal, which may begenerated in the PC or timing circuitry. The field sequence correctionsignal S_(COR) is output from the register 82 to the switch 84. With thecounter 86 set at “1”, the first delay number is sent to the delaycontrol circuit 88, which selects the delay tap within the bank of delaytaps 62 in accordance with the delay number. Until the field sequencegenerator 18 generates another field sequence correction signal S_(COR),the current field sequence correction signal S_(COR) is applied to theduplicated disrupted video signal VIDEO_(IN)′, with the counter 86counting from 1 to 5. In this manner, the delay numbers of the currentfield sequence correction signal S_(COR) are sequentially sent to thedelay control circuit 88, thereby sequentially delaying the selectedfields of the disrupted video signal VIDEO_(IN) to generate theundisrupted video signal VIDEO_(OUT) at the output 56. Thus, thecorrection signal S_(COR) is applied to the disrupted video signalVIDEO_(IN) in real time, i.e., at a field rate equal to the field rateof the disrupted video signal VIDEO_(IN).

It should be noted that although the 2-3 field pattern fixer 10 is shownas being selectively operated in a one-pass mode and a two-pass mode, itwill be readily apparent to those skilled in the art that a 2-3 fieldpattern fixer that is able to operate in only one of the modes can beconstructed without straying from the principles taught by thisinvention. For example, a 2-3 field sequence fixer that only operates ina one-pass mode obviates the need for circuitry that is otherwiserequired for the 2-3 field sequence fixer to operate in the two-passmode. Furthermore, operation of the 2-3 field sequence fixer solely inthe one-pass lends itself to a strict hardware implementation of the 2-3field sequence fixer, eliminating the need for a PC. In this connection,the field sequencer 16 and field sequence generator 18 can beimplemented in hardware, and the timecode comparator 14, timecode/fielddifference encoder 40, FIFO's 42 and 50, timecode/correction signaldecoder 52 and reset decoder 54 can be eliminated. In this case, thefield difference value ΔFD can be input directly into the field sequenceanalyzer 16 and the field sequence correction signal S_(COR) can beoutput directly from the field sequence generator 18.

While preferred methods and embodiments have been shown and described,it will be apparent to one of ordinary skill in the art that numerousalterations may be made without departing from the spirit or scope ofthe invention. Therefore, the invention is not to be limited except inaccordance with the following claims.

1. A method of generating an undisrupted video signal comprising aseries of fields arranged in a continuous 2-3 field sequence, the methodcomprising: receiving a disrupted video signal, the disrupted videosignal comprising a series of fields arranged in a discontinuous 2-3field sequence; analyzing the discontinuous 2-3 field sequence of thedisrupted video signal to determine a discontinuity; generating acorrection signal based on the determined discontinuity; and generatingthe undisrupted video signal by applying the correction signal to avideo signal.
 2. The method of claim 1, wherein the undisrupted videosignal is generated by rearranging the series of fields in one of thedisrupted video signal and a duplicate of the disrupted video signal inaccordance with the correction signal.
 3. The method of claim 1, whereinthe correction signal is applied to the disrupted video signal.
 4. Themethod of claim 3, wherein the received disrupted video signal isdelayed at least an amount of time required to generate the correctionsignal.
 5. The method of claim 3, wherein the correction signal isapplied to the video signal as the correction signal is generated. 6.The method of claim 1, wherein the correction signal is applied to aduplicate of the disrupted video signal.
 7. The method of claim 6,further comprising: determining a plurality of discontinuities in thediscontinuous 2-3 field sequence; determining a first plurality of timecodes within the disrupted video signal, the first plurality of timecodes respectively associated with the plurality of discontinuities;generating a plurality of correction signals respectively based on theplurality of discontinuities; receiving the duplicated disrupted videosignal; determining a second plurality of time codes within theduplicated disrupted video signal, the second plurality of time codescorresponding with the first plurality of time codes; and generating theundisrupted video signal by sequentially applying the plurality ofcorrection signals to the duplicated disrupted video signal as thecorresponding second plurality of time codes are determined.
 8. Themethod of claim 1, wherein the correction signal is generated byselecting a series of delays, each delay applied to one field of eitherthe disrupted video signal or a duplicate of the disrupted video signal.9. The method of claim 8, wherein a cumulative field delay is generatedwithin the undisrupted video signal, and wherein selection of the seriesof delays is based on a minimization of the cumulative field delay. 10.The method of claim 9, wherein the disrupted video signal includes aplurality of disjoined single field frames, and wherein selection of theseries of delays is based on discarding of the disjoined single fieldframes.
 11. The method of claim 10, wherein the discarding of disjoinedsingle field frames are based on a relative motion detected within thedisjoined single field frames.
 12. The method of claim 11, wherein thedisjoined single field frames having a relatively great motion arediscarded.
 13. The method of claim 11, wherein the disjoined singlefield frames having relatively little motion are discarded.
 14. Themethod of claim 1, wherein an edit point and a phase change within thediscontinuous 2-3 field sequence are determined, and the generation ofthe correction signal is based on the detected phase change and editpoint.
 15. The method of claim 14, wherein the edit point and a phase ofthe discontinuous 2-3 field sequence are determined by sequentiallycomparing fields twice removed in sequence.
 16. The method of claim 1,wherein a plurality of correction signals are generated and sequentiallyapplied to the video signal.
 17. The method of claim 1, wherein theapplication of the plurality of correction signals to the video signalgenerates a cumulative field delay between the discontinuous 2-3 fieldsequence of the disrupted video signal and the continuous 2-3 fieldsequence of the undisrupted video signal, and wherein the plurality ofcorrection signals are generated, such that the cumulative field delayis maintained within a range of selected values.
 18. A method ofcorrecting a disrupted video signal comprising a series of fieldsarranged in a discontinuous 2-3 field sequence, the method comprising:receiving the disrupted video signal; analyzing the discontinuous 2-3field sequence of the disrupted video signal to determine adiscontinuity; generating a correction signal based on the determineddiscontinuity; and generating the undisrupted video signal by applyingthe correction signal to a video signal at a field rate equal to thefield rate of the disrupted video signal.
 19. The method of claim 18,wherein the undisrupted video signal is generated by rearranging theseries of fields in either the disrupted video signal or the duplicateof the disrupted video signal in accordance with the correction signal.20. The method of claim 18, wherein the correction signal is applied tothe disrupted video signal.
 21. The method of claim 18, wherein thecorrection signal is applied to a duplicate of the disrupted videosignal.
 22. The method of claim 21, further comprising: determining aplurality of discontinuities in the discontinuous 2-3 field sequence;detecting a first plurality of time codes within the disrupted videosignal, the first plurality of time codes respectively associated withthe plurality of discontinuities; generating a plurality of correctionsignals respectively based on the plurality of discontinuities;receiving the duplicated disrupted video signal; detecting a secondplurality of time codes within the duplicated disrupted video signal,the second plurality of time codes corresponding with the firstplurality of time codes; and generating the undisrupted video signal bysequentially applying the plurality of correction signals to theduplicated disrupted video signal as the corresponding second pluralityof time codes are detected, each of the correction signals being appliedto the duplicated disrupted video signal at a field rate equal to afield rate of the disrupted video signal.
 23. The method of claim 18,wherein an edit point and a phase change within the discontinuous 2-3field sequence are determined, and the generation of the correctionsignal is based on the detected phase change and edit point.
 24. Themethod of claim 18, wherein a plurality of correction signals aregenerated and sequentially applied to the video signal, each of thecorrection signals being applied to the duplicated disrupted videosignal at a field rate equal to a field rate of the disrupted videosignal.
 25. A 2-3 field pattern fixer, comprising: a field sequencedetector configured for receiving a disrupted video signal having adiscontinuous 2-3 field sequence and generating a series of fielddifference values; a field sequence analyzer having an input coupled toan output of the field sequence detector and being configured forgenerating field sequence information based on the series of fielddifference values; a field sequence generator having an input coupled toan output of the field sequence analyzer and being configured forgenerating a sequence of delay numbers based on the field sequenceinformation; and a multiple delay tap circuit having an input coupled toan output of the field sequence generator and being configured forreceiving a video signal and for applying the sequence of delay numbersthereto to generate an undisrupted video signal having a continuous 2-3field sequence.
 26. The 2-3 field pattern fixer of claim 25, wherein thefield sequence analyzer and the field sequence generator are embodied ina computer.
 27. The 2-3 field pattern fixer of claim 25, wherein one ofthe field sequence generator and field sequence analyzer is furtherconfigured to receive a current time code of the disrupted video signaland generate a trigger time code in response thereto; wherein the 2-3field pattern fixer further comprises a time code comparator having anfirst input coupled to an output of the one of the field sequencegenerator and field sequence analyzer and a second input for receiving acurrent time code of the duplicated disrupted video signal, the timecode comparator configured for generating a trigger signal; and whereinthe multiple delay tap circuit includes a second input coupled to anoutput of the time code comparator, and configured for initiallyapplying the sequence of delay numbers to a duplicated of the disruptedvideo signal when the trigger signal equals a selected value.
 28. The2-3 field pattern fixer of claim 27, further comprising aFirst-In-First-Out (FIFO) memory device coupled between the fieldsequence generator and the multiple delay tap circuit; and wherein thefield sequence generator is configured for generating and storing aseries of correction signals within the FIFO.
 29. The 2-3 field patternfixer of claim 25, wherein the 2-3 field pattern fixer can beselectively operated in a one-pass mode and a two-pass mode.
 30. The 2-3field pattern fixer of claim 25, wherein the multiple delay tap circuitis implemented using RAM addressing circuitry.
 31. The 2-3 field patternfixer of claim 25, wherein the multiple delay tap circuit comprises abank of delay taps, and a delay tap selector coupled to the bank ofdelay taps for selecting one of the delay taps.
 32. The 2-3 fieldpattern fixer of claim 25, wherein the bank of delay taps comprises anodd delay tap with a cross-fader.
 33. A method of generating anundisrupted video signal comprising a series of fields arranged in acontinuous 2-3 field sequence, the method comprising: receiving adisrupted video signal, the disrupted video signal comprising a seriesof fields arranged in a discontinuous 2-3 field sequence; analyzing thediscontinuous 2-3 field sequence of the disrupted video signal todetermine a discontinuity within the discontinuous 2-3 field sequence;selecting a series of field delays based on the determineddiscontinuity; applying each field delay to one field of either thedisrupted video signal or a duplicate of the disrupted video signal togenerate the undisrupted video signal, wherein a field is delayed an oddnumber of fields; and cross-fading between the odd-delayed field andanother field to generate a field within the disrupted video signal. 34.The method of claim 33, wherein the cross-fading is between theodd-delayed field and an even-delayed field.
 35. The method of claim 34,wherein the odd-delayed field is at the beginning of a scene, andwherein the cross-fading is between the odd-delayed field and aneven-delayed field immediately subsequent to the odd-delayed field. 36.The method of claim 34, wherein the odd-delayed field is at the end of ascene, and wherein the cross-fading is between the odd-delayed field andan even-delayed field immediately preceding the odd-delayed field. 37.The method of claim 34, further comprising determining an absolute pixeldifference between the odd-delayed field and an immediately adjacentodd-delayed field, and wherein the odd-delayed field is faded to if theabsolute pixel difference is relative large and the odd-delayed field isfaded from if the absolute pixel difference is relatively small.
 38. Themethod of claim 37, further comprising delaying the absolute pixeldifference by one line and processing the absolute pixel difference andthe delayed absolute pixel difference to more accurately estimate anabsolute pixel difference between the odd-delayed field and animmediately adjacent even-delayed field.